.subckt mcp606 1 2 3 4 5 * | | | | | * | | | | Output * | | | Negative supply * | | Positive Supply * | Inverting input * Non-inverting input * * Macromodel for MCP606 (single), MCP607 (dual), MCP608 (single w/CS), * and MCP609 (quad) * ******************************************************************************** * Software License Agreement * * The software supplied herewith by Microchip Technology Incorporated (the * * "Company") is intended and supplied to you, the Company's customer, for use * * solely and exclusively on Microchip products. * * * * The software is owned by the Company and/or its supplier, and is protected * * under applicable copyright laws. All rights are reserved. Any use in * * violation of the foregoing restrictions may subject the user to criminal * * sanctions under applicable laws, as well as to civil liability for the * * breach of the terms and conditions of this license. * * * * THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER * * EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED * * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO * * THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR * * SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************** * * The characteristics of the MCP606, MCP607, MCP608, and MCP609 have the same * fundamental performance and behavior. Consequently, this single op amp * macromodel supports all four devices. However, the chip select function of * the MCP608 is not modeled. * * Revision History: * REV A : 6-30-99 created BCB * * This macromodel models typical amplifier offset voltage, DC power supply * rejection, input capacitance, open loop gain over frequency, phase margin * with 60pF load, output swing, power supply current, input voltage noise, * slew rate. * *Input Stage, pole at 300kHz M1 9 64 7 3 Ptype M2 8 2 7 3 Ptype CDIFF 1 2 3E-12 CCM1 1 4 6E-12 CCM2 2 4 6E-12 IDD 3 7 13.33e-6 RA 8 6 1.839e3 RB 9 6 1.839e3 CA 8 9 125e-12 ICOMP 3 4 -194.63e-6 *Input Stage Common-Mode Clamping VCMM 4 6 0.35 ECM 55 4 3 64 1 RCM 57 56 1E3 DCMP 56 55 DY VCMP 57 4 1.2 RST 58 59 1E3 DST 59 55 DX VST 58 4 1.6 GCMP2 23 4 POLY(2) 57 56 58 59 0 0 0;0 -0.5E-3 0.5E-3 *Input errors (vos, en, psr) ERR 64 1 poly(2) (67,4) (3, 4) -229.9e-6 1 23e-6 *Second Stage, pole at 0.183Hz GS 23 4 8 9 543.78e-6 R1 23 4 8.2144e9 C2 23 4 110e-12 VSOM 3 24 4.784 VSOP 25 4 -3.98 DSOM 23 24 DY DSOP 25 23 DY *HCM 23 3 VCMP FS 3 4 POLY(11) VO3 VO5 VO4 VO6 VO1 VO2 VO9 VO10 VMID1 VSOP VSOM + 200E-6 -1 -1 -1 1 -1 -1 1 1 -1 -1 -1 *mid-supply reference RMID1 3 35 61.62E3 VMID1 35 34 0 RMID2 4 34 61.62E3 ELEVEL 34 4 23 4 -1 *output stage DO3 34 43 DY DO4 44 34 DY DO5 3 45 DY DO6 3 46 DY DO7 4 45 DY DO8 4 46 DY VO3 43 5 0.1 VO4 5 44 0.03 GO5 3 47 3 34 10E-3 VO5 47 5 0 GO6 4 48 34 4 10E-3 VO6 48 5 0 GO1 49 4 5 34 10E-3 VO1 49 45 0 GO2 50 4 34 5 10E-3 VO2 50 46 0 RO9 3 51 100 VO9 51 5 0 RO10 52 4 100 VO10 52 5 0 * input voltage noise VN1 65 4 0.6 DN1 65 67 DX RN1 67 4 10E3 .model Ptype PMOS L=2 W=105 .model DY D (IS=1e-15 BV =50) .model DX D (IS=1e-18 AF=0.6 KF=10e-17) .ENDS