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Pasadena, California - July 27, 2005 - Tanner EDA today announced the release of T-Spice v11, the company’s analog circuit simulation platform. This newest release adds support for the latest Berkeley BSIM models up to the v4.4.0 release that allow users to accurately simulate MOSFET physical effects down to the sub-100 nanometer range. This latest release also supports numerous advanced modelling features to improve simulation accuracy.
New modelling features supported include gate and body resistance networks for RF modelling, non-quasi-static (NQS) model, comprehensive geometry-based parasitic models for multi-finger devices, and stress effects modelling.
Support for BSIM SOI v3.2 helps designers using the SOI CMOS process. It allows them to accurately model partially depleted, fully depleted and unified FD-PD SOI devices. Self-heating and RF resistor networks can also be modelled. MOSFET EKV support assists designers needing a continuous, physics based MOSFET model for low power analog and mixed analog-digital circuit design.
Tanner EDA’s T-Spice v11 also includes improvements to the VBIC model with addition of self-heating effects and improvements to BSIM3 v3.2.4 including stress effects modelling and enhanced diode and temperature equations. These functions improve compatibility with many foundry model libraries.
Product Availability T-Spice V11 is available now. For further pricing and product information, please email sales@tanner.com or call +1-877-325-2223.
