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As design teams adopt nanometer process technologies they face a new set of design challenges referred to as nanometer effects. These nanometer effects include:
Dramatic increases in the number of transistors in the design adding to design complexity
Smaller transistor sizes leading to larger leakage currents and greater power consumption
More pronounced non-linear transitions on the devices increasing leakage currents
Tighter cross-coupling inducing noise and delay problems.
To analyze and manage these issues design teams must be able to accurately simulate the impact these effects will have on their design.
Historically, design teams have relied on SPICE as the “golden” reference point against which accuracy is typically measured. SPICE simulators use a single voltage-based evaluation engine to simulate every entity in the design. As size and the complexity of designs increased its speed and capacity limitations surfaced. To address these limitations the next-generation of hierarchical or “Fast-SPICE” simulators were introduced. Because they still use a single voltage-based evaluation engine, these simulators address the capacity issues by breaking up a design (a single large matrix) into lots and lots of smaller matrices. While this helped address the capacity and speed issues it presented several drawbacks:
Many nanometer design issues are current-based (power, noise, electro-migration, and power supply variation), not voltage-based
Segmenting a design is fine for memories which contain lots of hierarchical entities, but not much good when simulating large digital or analog designs
Accuracy is typically only within 4 or 5% of SPICE. Fast-SPICE simulators sacrifice accuracy for increased speed and capacity
Nascim is a 3rd generation simulation engine that overcomes these limitations and drawbacks. Using patent-pending, current-based transistor, cell, and interconnect models, Nascim executes tens of thousands of times faster than SPICE, and dozens of time faster than Fast-SPICE simulators. The intelligent transformation and efficient processing of design entities (diodes, inductors, transistor, cells, interconnect, and so on) provides the capacity to handle large memory and digital logic designs. To ensure accuracy, Nascim employs a variety of evaluation engines specifically tuned to the unique simulation requirements of each design entity. Working seamlessly these engines provide the speed and accuracy needed to address the multi-faceted nanometer design issues involved in predicting actual silicon performance.
