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An empirical sub-circuit was implemented in PSPICEŽ and is presented. It accurately portrays the vertical DMOS power MOSFET electrical and for the first time, thermal responses. Excellent agreement is demonstrated between measured and modeled responses including first and third quadrant MOSFET and gate charge behavior, body diode effects, breakdown voltage at high and low currents, gate equivalent series resistance, and package inductances for temperatures between -55 °C and 175 °C. Parameter extraction is relatively straight forward as described.
