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SiAuditor was developed in concert with Core-to-Core to meet the needs of high-speed designers. It utilizes the industry-standard Hspice simulation engine, and includes integrated waveform and timing analysis, as well as advanced data management. SiAuditor is the only tool to seamlessly integrate IBIS and Hspice models, as well as support complete design analysis reuse.
Integrated Waveform and Timing Analysis SiAuditor provides the industry's most rigorous waveform processing; checking every edge of every simulation. It supports all IBIS waveform rules plus several additional rules to ensure proper I/O buffer operation. Variables such as IC process, etch process, and environmental extremes are also analyzed; as well as probe points at the pin, pad, and core. And both synchronous and source-synchronous clocking are supported.
Advanced Data Management The software provides consistency checking across libraries and design inputs. Data is entered, checked, and used in one place, and shared between projects. SiAuditor facilitates complete design analysis reuse; leveraging intellectual property and improving productivity.
Design Analysis Reuse SiSoft has created and patented an implementation independent net list description (Transfer Net List). This novel approach describes how devices are connected at a level of abstraction that automatically maps both the logical and physical implementation to the Transfer Net List. In other words, the critical reusable information is inherent in the data structure; akin to "electrical DNA", facilitating easy reuse of analyzed data.
SiAuditor also supports a common simulation environment for both pre-layout and post-layout analysis, including:
Automatic setup of the post-layout simulations. For instance, environmental conditions, noise limits, input stimulus, measurement conditions, and measurement nodes are directly inherited from the pre-layout environment.
Behavioral and transistor level models
Single and multi-board extraction of networks from a mixture of host CAD systems.
